The use of FPGAs for carrying out high speed DPS arithmetic computations has gained recognition in recent years. FPGAs having architectures which include logic blocks having multiple look-up-table function generators, such as the XC4000.TM. family of devices from XILINX, Inc., the assignee herein, are particularly suited for such computations. However, many of the important DSP algorithms are multiply-intensive, and even the FPGAs having the largest number of logic blocks, normally can't embed the multiplier circuits and the attendant control and support circuits in a single chip. It becomes incumbent on the designer to choose efficient DSP algorithms and to realize them with efficient circuit designs. The FFT is an outstanding example of an efficient DSP algorithm and distributed arithmetic is a well established design approach that replaces gate-consuming array multipliers with efficient shift and add equivalent circuits that offer comparable performance.
FFT--The discrete Fourier transform (DFT) of a sampled time series is closely related to the Fourier transform of the continuous waveform from which the time samples were taken. The DFT is thus particularly useful for digital power spectrum analysis and filtering. The FFT is a highly efficient procedure for computing the DFT of a time series and was reported by Cooley and Tukey in 1965 ("AN ALGORITHM FOR THE MACHINE CALCULATION OF COMPLEX FOURIER SERIES" by J. W. Cooley and J. W. Tukey, Math of Comput., Vol. 19, pp. 297-301, April 1965).
It takes advantage of the fact that the calculation of the coefficients of the DFT can be carried out interactively, which results in a considerable savings of computation time. If the time series contains N=2.sup.n samples, then for the N Fourier coefficients the FFT entails 2nN=2N log.sub.2 N multiply operations (assuming a radix 2 butterfly). In contrast, the DFT algorithm requires N.sup.2 multiply operations. The FFT advantage grows as N increases. Thus an 8 point DFT and FFT require 64 and 48 multiply operations, respectively, while an 8192 point DFT and FFT require 67.1.times.10.sup.6 and 212,384 multiply operations, respectively.
Distributed Arithmetic (DA)--Distributed Arithmetic was developed as an efficient computation scheme for digital signal processing (DSP). A United States patent describing this scheme is 1974 (U.S. Pat. No. 3,777,130 issued Dec. 3, 1974 entitled "DIGITAL FILTER FOR PCM ENCODED SIGNALS" by Croisier, D. J. Esteban, M. E. Levilion and V. Rizo. A comprehensive survey of DA applications in signal processing was made by White ("APPLICATIONS OF DISTRIBUTED ARITHMETIC TO DIGITAL SIGNAL PROCESSING: A TUTORIAL REVIEW" by S. A. White, IEEE ASSP Magazine, July 1989).
The distributed arithmetic computation algorithm is now being effectively applied to embed DSP functions in FPGAs, particularly those with coarse-grained look-up table architecture. Practical FIR, IIR and small size FFT designs have been developed. DA enables the replacement of the array multiplier, central to all these applications, with a gate-efficient serial/parallel multiplier with little or no reduction in speed.
DA makes extensive use of look-up tables (LUT's), thereby fully exploiting the LUT-based architecture of the Xilinx and other similarly structured FPGAs. The LUT used in a DA circuit will hereafter be called a DALUT. One can use a minimum set of DALUTs and adders in a sequential implementation to minimize cost. However, speed/cost tradeoffs can be made. Specifically, for higher speed, more DALUTs and adders may be employed. With enough DALUTs and adders, the range of tradeoffs extends to full parallel operation with all input bits applied simultaneously to the DALUTS and an output response generated at each system clock.
Distributed arithmetic differs from conventional arithmetic only in order in which it performs operations. The transition from conventional to distributed arithmetic is illustrated in FIGS. 1, 2 and 3. In FIG. 1 which illustrates conventional arithmetic, the sum of products equation, S=A.cndot.K+B.cndot.L+C.cndot.M+D.cndot.N is implemented with 4 serial/parallel multipliers operating concurrently to generate partial products. The full products are then summed in an adder tree to produce the final result, S. The functional blocks of the serial/parallel multiplier shown in the box of FIG. 1 include an array of 2-input AND gates with the A input derived from a parallel to serial shift register and the K input applied bit-parallel to all AND gates. A P bit parallel adder accepts the AND gate outputs addend inputs and passes the sum to an accumulator register. A divide by 2 block feeds back the register output to the augend inputs of the adder. In each clock cycle one bit of the serially organized data (Ai, Bi, Ci, Di) is ANDed with parallel operands (K, L, M, N) and four partial products are generated. Starting with the least significant serial bits, the partial products are stored in the four accumulator registers. On the next clock cycle, the next least significant bits again form partial products which are then added to the scaled by 1/2 previous partial product. The process repeats on successive clock cycles until the most significant bits have been shifted. When all the partial products, appropriately scaled, have been accumulated, they are fed to the adder array to produce the final output, S. Distributed arithmetic adds the partial products before, rather than after, scaling and accumulating them.
FIG. 2 shows the first embodiment of the distributed arithmetic technique. The number of shift and add circuits is reduced to one and is placed at the output of the array of simple adders, the number of simple adders remains the same. The two-input AND gates now precede the adders.
In a very important class of DSP applications known as linear, time-invariant systems the coefficients (K, L, M and N in our example) are constants. Consequently, the data presented to the shift-and-add circuit; namely, the output of the AND gates and the three simple adders depend only on the four shift register output bits. Replacing the AND gates and simple adders with a 16 word look-up table (DALUT) provides the final form (FIG. 3) of the distributed arithmetic implementation of the sum of products equation.
The DALUT contains the pre-computed values of all possible sums of coefficients weighted by the binary variables of the serial data (A, B, C and D) which previously constituted the second input to the AND gates. Now, with the four serial data sources serving as address lines to the DALUT, the DALUT contents may be tabulated as follows:
______________________________________ A B C D Address Content ______________________________________ 0 0 0 0 0 0 0 0 0 1 1 N 0 0 1 0 2 M 0 0 1 1 3 M + N 0 1 0 0 4 L 0 1 0 1 5 L + N 0 1 1 0 6 L + M 0 1 1 1 7 L + M + N 1 0 0 0 8 K 1 0 0 1 9 K + N 1 0 1 0 10 K + M 1 0 1 1 11 K + M + N 1 1 0 0 12 K + L 1 1 0 1 13 K + L + N 1 1 1 0 14 K + L + M 1 1 1 1 15 K + L + M + N ______________________________________
In general, the length or number of words in the DALUT is 2.sup.a where "a" is the number of address lines. The width, or number of bits per word cannot be precisely defined; it has an upper limit of b+log 2a due to computation word growth where the coefficients are summed, as the content of the DALUT indicates (wherein b is the number of coefficient bits). The width of the table defines the coefficient accuracy and may not match the number of signal bits (e.g., the bits of A, B, C, and D) which define the dynamic range or linearity of the computation process.
Large FFTs in a Single FPGA--Now that the array multiplier has been replaced by a gate-efficient distributed circuit, there remains a second obstacle to overcome before a large size FFT can be practically embedded in a single FPGA, namely, the large memory required for the sine/cosine basis functions. An 8192 point FFT, for example, requires 8192 basis words and a look-up table capacity of 65,536 is needed for 16 bit accuracy. The Xilinx XC4000.TM. FPGA family with configurable logic blocks (CLBs) articulated as 32.times.1 look-up tables would require 131072/32 or 4096 CLBs. This number is almost double the CLB capacity (2,304) of the XC4062XL.TM. chip, currently the largest device in the XC400.TM. family.
It would be economically advantageous to provide a method for configuring smaller, less costly FPGAs such as the Xilinx XC4025.TM. device to perform 8192 or larger point FFTs and other vector rotations.
Those having skill in the relevant arts, will recognize that the invention hereinafter disclosed has some aspects which may be considered related to vector rotation iterations used in CORDIC processors, wherein CORDIC stands for Coordinate Rotation Digital Computer as disclosed in U.S. Pat. No. 5,371,753, assigned to Kuenemund et al. The CORDIC algorithm is similar to the invention disclosed in that both compute vector rotations 4096 words and cannot be reduced by any known interpolation scheme. A CORDIC FFT processor cannot be realized in a single FPGA.